1. Field of the Invention
This invention relates generally to semiconductor input/output drivers, and more particularly to voltage tolerant circuits for protecting input buffers in semiconductor input/output drivers.
2. Description of the Related Art
In today's world of smaller process geometries, board voltages have not kept up with chip voltages. As a result, there is a need for tolerant input/output (I/O) designs that can tolerate higher voltages on the boards than the voltages used for internal operation of the chips. That is, the input section of an I/O circuit generally requires some form of protection. For example, FIG. 1 shows an exemplary printed circuit board (PCB) configuration 100. The PCB configuration 100 includes a PCB 102 and a plurality of chips 104a-104b disposed on the PCB 102. Each chip 104a-104b includes an I/O ring 106a-106b that provides I/O operations for the chip 104a-104b. Although only two chips 104a-104b are illustrated in FIG. 1, it should be borne in mind that a typical PCB configuration 100 will include many chips 104a-104b disposed throughout the PCB 102.
The various chips on the PCB 102 can operate at different voltages. For example, chip 104a can be a 0.13 micron chip that operates at 1.2 volts, and chip 104b can be a 0.25 micron chip that operations at 2.25 volts. As can be appreciated, a voltage mismatch occurs when chip 104b drives a signal at 2.25 volts, but chip 104a only has a 1.2 volt internal supply. Thus, the I/O devices within the I/O rings 106a-106b must be specially designed to handle the voltage mismatch.
The I/O rings 106a-106b generally have voltages greater than the internal supply voltages of the chips. For example, the ring voltage of I/O ring 106a can be, for example, 3.3 volts, and the ring voltage of I/O ring 106b can be, for example, 5 volts. Thus, in the above example, the I/O ring 106b of chip 104b provides a 5 volt signal to the I/O ring 106a of chip 104a, which operates at 3.3 volts.
Conventionally, a single N-pass gate could be used as a voltage tolerant I/O circuit. FIG. 2A is a schematic diagram showing a prior art N-pass gate I/O circuit 200. The N-pass gate I/O circuit 200 includes an n-channel transistor 202 having a first terminal coupled to a pad I/O 210, a second terminal coupled to an input buffer 204, and a gate coupled to the ring voltage, referred to as the ring VDD. Although, the input buffer 204 illustrated in FIG. 2A is an inverter, it should be noted that the N-pass gate I/O circuit 200 can be utilized with any type of input device, such as a differential pair.
Because transistor 202 is an n-channel transistor, the highest voltage that can occur at node 206 is Ring VDD−VTn, regardless of the voltage applied at pad I/O 210. Thus, the prior art N-pass gate I/O circuit 200 will operate properly if VDD−VTn is high enough to fully turn on and off the input buffer 204. However, a leakage current typically occurs when utilizing the a prior art N-pass gate I/O circuit 200, as illustrated next in FIG. 2B.
FIG. 2B is a timing diagram 250 showing voltage and current levels during operation of the prior art N-pass gate I/O circuit. The timing diagram 250 illustrates the voltage levels of the pad I/O 210, node 206, node 208, and the current level 252 within the input buffer 204 when the pad I/O 210 rises from LOW to HIGH. As illustrated in FIG. 2B, when the pad I/O 210 is LOW, node 206 is LOW and node 208 is HIGH because of inverter 204. When the pad I/O 210 transitions to a HIGH state, the voltage on node 206 rises to Ring VDD−VTn. As mentioned above, the highest voltage that can occur at node 206 is Ring VDD−VTn, regardless of the voltage applied at pad I/O 210, because transistor 202 is an n-channel transistor. The Ring VDD−VTn voltage at the input of the inverter 204 causes node 208 to transition to a LOW voltage. However, if VDD−VTn is not high enough to fully turn off the p-channel transistor in the input buffer 204, a leakage current can result. The current level 252 illustrates the crossover current that occurs during switching of the CMOS transistors. As can be seen, if VDD−VTn is not high enough to fully turn off the p-channel transistor in the input buffer 204, a leakage current 254 can remain after the pad I/O 210 goes HIGH. To address this issue, a keeper circuit can be utilized with the I/O circuit.
FIG. 3A is a schematic diagram showing a prior art keeper based I/O circuit 300. The keeper based I/O circuit 300 includes an n-channel transistor 302 having a gate coupled to Ring VDD, a first terminal coupled to a pad I/O 310, and a second terminal coupled to node 306, which is coupled to an input buffer 304. The output of the input buffer 304 is coupled to the gate of a p-channel keeper transistor 312, which includes a first terminal coupled to Ring VDD and a second terminal coupled to node 306. As above, it should be noted that the input buffer 304 can be any type of input device, such as a differential pair.
In operation, when the pad I/O 310 goes high, transistor 302 raises the voltage on node 306 to Ring VDD−VTn. As mentioned above, because transistor 302 is an n-channel transistor, the highest voltage that can occur at node 306 is Ring VDD−VTn, regardless of the voltage applied at pad I/O 310. The inverter 304 begins to pull node 308 LOW, which places a LOW at the gate of transistor 312, turning transistor 3120N. In response, transistor 312 pulls up node 306 to Ring VDD. As a result, node 306 is made HIGH enough to switch inverter 304. Unfortunately, the keeper transistor 312 slows the I/O circuit 300 down when the pad 310 goes LOW.
FIG. 3B is a timing diagram 350 showing voltage and current levels during operation of the prior art keeper based I/O circuit. The timing diagram 350 illustrates the voltage levels of the pad I/O 310, node 306, node 308, and the current level 352 within the input buffer 304 when the pad I/O 310 rises from LOW to HIGH. As illustrated in FIG. 3B, when the pad I/O 310 is LOW, node 306 is LOW and node 308 is HIGH because of inverter 304. When the pad I/O 310 transitions to a HIGH state, the voltage on node 306 rises to Ring VDD in a stepwise manner. In particular, the voltage on node 306 initially rises to Ring VDD−VTn, illustrated at point 354 when the pad I/O goes HIGH. Then, the keeper p-channel transistor 312 allows current to flow from Ring VDD to node 306, raising the voltage at node 306 to Ring VDD at point 356. The Ring VDD voltage at node 306 is then high enough to turn. OFF the p-channel transistor within the inverter 304 and turn ON the n-channel transistor in the inverter 304, thus allowing node 308 to fall to zero volts. As illustrated by the graph of the crossover current 352, the prior art keeper based I/O circuit prevents leakage from occurring. Unfortunately, the keeper p-channel transistor 312 of the prior art keeper based I/O circuit 300 slows down the switching time for the input circuit because the keeper p-channel transistor 312 must be overcome to transition the voltage on node 306 from HIGH to LOW.
In view of the foregoing, there is a need for a voltage tolerant circuit for protecting an input buffer. The voltage tolerant circuit should not produce a leakage current, allow fast switching, and should not pump current back into the pad.